Micron Technology DRAM SDRAM-DDR4, Part #MT40A2G4SA-075:E TR

Features: 

• VDD = VDDQ = 1.2V ±60mV
• VPP = 2.5V –125mV/+250mV
• On-die, internal, adjustable VREFDQ generation
• 1.2V pseudo open-drain I/O
• Refresh maximum interval time at TC temperature range: – 64ms at –40°C to 85°C – 32ms at 85°C to 95°C – 16ms at 96°C to 105°C – 8ms at 106°C to 125°C
• 16 internal banks ( x8): 4 groups of 4 banks each
• 8 internal banks (x16): 2 groups of 4 banks each
• 8n-bit prefetch architecture
• Programmable data strobe preambles
• Data strobe preamble training
• Command/Address latency (CAL)
• Multipurpose register read and write capability
• Write leveling
• Self refresh mode
• Low-power auto self refresh (LPASR)
• Temperature controlled refresh (TCR)
• Fine granularity refresh
• Self refresh abort
• Maximum power saving
• Output driver calibration
• Nominal, park, and dynamic on-die termination (ODT)
• Data bus inversion (DBI) for data bus
• Command/Address (CA) parity
• Databus write cyclic redundancy check (CRC)
• Per-DRAM addressability
• Connectivity test
• Hard post package repair (hPPR) and soft post package repair (sPPR) modes
• JEDEC JESD-79-4 compliant

MIL:MT40A2G4SA-075:E TR

MT40A2G4SA-075:E TR